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| ICS525-03 PECL Input OSCaRTM User Configurable Clock Description The ICS525-03 are the most flexible way to generate a high-quality, high-accuracy, high-frequency clock output from a PECL input. The name OSCaR stands for OSCillator Replacement, as they are designed to replace crystal oscillators in almost any electronic system. The user can configure the device to produce nearly any output frequency from any input frequency by grounding or floating the select pins. Neither microcontroller, software, nor device programmer are needed to set the frequency. Using Phase-Locked Loop (PLL) techniques, the device accepts a PECL clock to produce output clocks up to 250 MHz, keeping them frequency locked together. Resistors are for PECL outputs only. For simple multipliers to produce common frequencies, refer to the LOCOTM family of parts, which are smaller and more cost effective. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. Features * Packaged as 28-pin SSOP (150 mil body) * Highly accurate frequency generation * User determines the output frequency by setting all * * * * * * * * * * * * internal dividers Eliminates need for custom oscillators No software needed Pull-ups on all select inputs PECL input clock frequency of 0.5 to 250 MHz Output clock frequencies up to 250 MHz Very low jitter Operating voltage of 3.0 V or 5.5 V 25 mA drive capability at TTL levels Ideal for oscillator replacement Industrial temperature Available in Pb (lead) free package Advanced, low-power CMOS process Block Diagram 2 VDD VDD 62 Ohm CLK1 PECLIN PECLIN Reference Divider Phase Comparator, Charge Pump, and Loop Filter VCO Divider VCO Output Divider 270 Ohm VDD 62 Ohm CLK2 7 R6:R0 2 GND 9 V8:V0 3 S2:S0 270 Ohm RES MDS 525-03 H Integrated Circuit Systems, Inc. 1 525 Race Street, San Jose, CA 95126 Revision 010906 tel (408) 297-1201 www.icst.com ICS525-03 PECL Input OSCaRTM User Configurable Clock Pin Assignment R5 R6 S0 S1 S2 VDD PECL PECLIN GND V0 V1 V2 V3 V4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R4 R3 R2 R1 R0 VDD CLK2 CLK1 GND RES V8 V7 V6 V5 RES Value Table RES 0 1.1 k Resistor to VDD CLK1 CMOS PECL CLK2 CMOS PECL Pre-divide (P) 2 1 28-pin SSOP Output Divider and Maximum Output Frequency Table S0 pin 5 0 0 0 0 1 1 1 1 S1 pin 4 0 0 1 1 0 0 1 1 S2 pin 3 0 1 0 1 0 1 0 1 CLK Output Divider (OD) 6 2 8 4 5 7 1 3 RES = 0 67 200 50 100 80 57 250 133 Max. Output Frequency (MHz) VDD = 5 V RES = 1.1 k 34 100 25 50 40 29 200 80 40 120 30 60 48 34 200 80 VDD = 3.3 V RES = 0 RES = 1.1 k 20 60 15 30 24 17 125 40 Note: 0 = connect directly to ground; 1 = connect directly to VDD. MDS 525-03 H Integrated Circuit Systems, Inc. 2 525 Race Street, San Jose, CA 95126 Revision 010906 tel (408) 297-1201 www.icst.com ICS525-03 PECL Input OSCaRTM User Configurable Clock Pin Descriptions Pin Number 1, 2, 24-28 3, 4, 5 6, 23 7 8 9, 20 10 - 18 19 21 22 Pin Name R5, R6, R0-R4 S0, S1, S2 VDD PECLIN PECLIN GND V0 - V8 RES CLK1 CLK2 Pin Type I(PU) I(PU) Power Input Input Power I(PU) Input Output Output Pin Description Reference divider word input pins determined by user. Forms a binary number from 0 to 127. Select pins for output divider determined by user. See table above. Connect to VDD. PECL input. Complementary PECL input. Connect to ground. VCO divider word input pins determined by user. Forms a binary number from 0 to 511. Select eithe PECL or CMOS outputs. See table above. Output clock. Either PECL or CMOS determined by RES. Output clock. Either PECL or CMOS determined by RES. KEY: I(PU) = Input with internal pull-up resistor. Output Clock Selection If RES is connected directly to ground, CLK1 and CLK2 are low skew, CMOS outputs clocks. They are not complementary. If RES is connected to VDD through a 1.1 k resistor, then CLK1 and CLK2 become complementary PECL outputs which require the external resistor network shown in the the block diagram. Refer to Application Note MAN09 for additional information. MDS 525-03 H Integrated Circuit Systems, Inc. 3 525 Race Street, San Jose, CA 95126 Revision 010906 tel (408) 297-1201 www.icst.com ICS525-03 PECL Input OSCaRTM User Configurable Clock External Components/Crystal Selection Decoupling Capacitors The ICS525-03 requries two 0.01F decoupling capacitors to be connected between VDD and GND, one on each side of the chip. The capacitor must be connected close to the device to minimize lead inductance. No external power supply filtering is required for this device. Also, the following operating ranges should be observed: 10 MHz < Input frequency x P x (VDW+8) <350 MHz at 5.0 V or (RDW+2) <250 MHz at 3.3 V 200 kHz < Input Frequency (RDW+2) (See table on page 2 for full details of maximum output) The dividers are expressed as integers, so that if a 66.66 MHz PECL output is desired from a 14.31818 PECL input, the Reference Divider Word (RDW) should be 59 and the VCO Divider Word (VDW) should be 276, with an Output Divider (OD) of 1. To select PECL outputs, the RES pin should be tied to VDD with a 1.1k resistor. In this example, R6:R0 is 100010100, and S2:S0 is 110. Since all of these inputs have pull-up reistors, it is only necessary to ground the zero pins, namely V7, V6, V5, V3, V1, V0, R6, R2 and S0. To determine the best combination of VCO, reference, and output divide, use the ICS525 Calculator on our web site: www.icst.com/products/ics525inputForm.html. The online form is easy to use and quickly shows you up to three options for these settings. Alternately, you may send an e-mail to ics-mk@icst.com. External Resistors If PECL outputs are desired, RES should be tied to VDD with a 1.1 k resistor. Each output needs a resistive network of 62 and 270 per the block diagram on page 1. Application note MAN09 gives more information about resistor selection. Determining (setting) the Output Frequency Users have full control in setting the desired output frequency over the range shown in the table on page 2. To replace a standard oscillator, users should connect the divider select input pins directly to ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit Board layout. The ICS525-03 will automatically produce the correct clock when all components are soldered. It is also possible to connect the inputs to parallel I/O ports to switch frequencies. By choosing divides carefully, the number of inputs which need to be changed can be minimized. Observe the restrictions on allowed values of VDW and RDW. The output of the ICS525-03 can be determined by the following simple equation: CLK Frequency = Input Frequency x Px -------------------------------------------- ( VDW + 8 ) ( RDW + 2 ) * OD Where: Reference Divider Word (RDW) = 0 to 127 VCO Divider Word (VDW) = 0 to 511 Output Divider (OD) = values on page 2 Pre-divide (P) = values on page 2 under RES Value Table MDS 525-03 H Integrated Circuit Systems, Inc. 4 525 Race Street, San Jose, CA 95126 Revision 010906 tel (408) 297-1201 www.icst.com ICS525-03 PECL Input OSCaRTM User Configurable Clock Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS525-03. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature, Industrial Storage Temperature Junction Temperature Soldering Temperature 7V Rating -0.5 V to VDD+0.5 V -40 to +85C -65C to 150C 125C 260C (max. of 10 seconds) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V Parameter Operating Voltage Operating Supply Current Operating Supply Current, LVPECL mode Input High Voltage Input Low Voltage Peak-to-peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage Short Circuit Current Input Capacitance On-chip Pull-up Resistor Symbol VDD IDD IDD VIH VIL Conditions 60 MHz out, no load With termination resistors Min. 3.0 Typ. 15 35 Max. 5.5 Units V mA mA V 2 0.8 PECLIN, PECLIN PECLIN, PECLIN 0.3 VDD-1.4 2.4 0.4 70 4 270 1 VDD-0.6 V V VOH VOL IOH = -25 mA, CMOS out IOL = 25 mA, CMOS out CMOS out V V mA pF k CIN RPU V, R, S select pins V, R, S select pins MDS 525-03 H Integrated Circuit Systems, Inc. 5 525 Race Street, San Jose, CA 95126 Revision 010906 tel (408) 297-1201 www.icst.com ICS525-03 PECL Input OSCaRTM User Configurable Clock AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V Parameter Input Frequency Output Frequency, VDD=4.5 to 5V Output Frequency, VDD=3.0 to 3.6 V Output Clock Rise Time, CMOS clock Output Clock Fall Time, CMOS clock Output Clock Duty Cycle, even output dividers Output Clock Duty Cycle, odd output dividers Absolute Clock Period Jitter One Sigma Clock Period Jitter Symbol FIN FOUT FOUT Conditions Clock input OD = 1 OD = 1 0.8 to 2.0 V 2.0 to 0.8 V at VDD/2 at VDD/2 Min. 0.5 1 1 Typ. Max. 250 250 200 Units MHz MHz MHz ns ns 1 1 45 40 350 125 55 60 % % ps ps tja tjs Deviation from mean One Sigma MDS 525-03 H Integrated Circuit Systems, Inc. 6 525 Race Street, San Jose, CA 95126 Revision 010906 tel (408) 297-1201 www.icst.com ICS525-03 PECL Input OSCaRTM User Configurable Clock Package Outline and Package Dimensions (28-pin SSOP, 150 mil Body) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 28 Millimeters Symbol E1 INDEX AREA E Inches Min Max Min Max 12 D A 2 A 1 A A A1 A2 b C D E E1 e L aaa 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 9.80 10.00 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0 8 -0.10 .053 .069 .0040 .010 -.059 .008 .012 .007 .010 .386 .394 .228 .244 .150 .157 0.025 Basic .016 .050 0 8 -0.004 c -Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number ICS525R-03I ICS525R-03IT ICS525R-03ILF ICS525R-03ILFT Marking ICS525R-03I ICS525R-03I ICS525R-03ILF ICS525R-03ILF Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP Temperature -40 to +85C -40 to +85C -40 to +85C -40 to +85C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments MDS 525-03 H Integrated Circuit Systems, Inc. 7 525 Race Street, San Jose, CA 95126 Revision 010906 tel (408) 297-1201 www.icst.com |
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